As shown in the block diagram of FIG. 1, a conventional circuit 10 comprises a transport overhead/path overhead generator 12, a transport overhead/path overhead extractor 14, and a path and transport overhead processor 16. The path and transport overhead processor 16 receives or generates a relatively large set of data communications signals. The path and transport overhead processor 16 comprises a path overhead interface 18, a transport overhead interface 20, a path overhead interface 22 and a transport overhead interface 24. The path overhead interface 18 comprises a number of signals TPOH, TPOHEN, TPOHCLK and TPOHFP, and receives or generates signals RPOH, RPOHCLK and RPOHFP. Transmit and receive path overhead pins (e.g., “TPOH” and “RPOH”) are for respectively transmitting data to and receiving data from the path and transport overhead processor 16. The path overhead and transport processor 16 transmits and receives path overhead clocks (e.g., RPOHCLK and TPOHCLK), transport overhead clocks (e.g., TTOHCLK and RTOHCLK), transport overhead enable signals (e.g., XTOHEN), and start of the payload indicators (e.g., TPOHFP). The path overhead enable pin (e.g., TPOHEN) for the path overhead generator 12 indicates whether or not the current path overhead bytes should be used.
In this methodology, a separate interface is provided for transport overhead communication. For the transmit side, a transmit path frame signal TPOHFP is asserted by the path and transport overhead processor 16 to synchronize the generator 12 and the processor 16. Once the path overhead generator 12 detects an asserted signal on the TPOHFP pin, all the path overhead bytes serially shift out on the data pin TPOH. This serial shifting of the data is timed and/or controlled by a clock signal (e.g., TPOHCLK).
For the receive side, the path overhead processor 16 asserts a receive frame signal (e.g., RPOHFP) in order to indicate to the path overhead extractor 14 that the path overhead is ready and is being presented on the data pin (e.g., RPOH). Data extraction operations are timed and/or controlled by a clock (e.g., RPOHCLK).
A significant disadvantage of this conventional methodology is the relatively high pin count resulting from the separate transport overhead interfaces 20 and 24 and the path overhead interfaces 18 and 22. For multiple framer chips (e.g., having 2, 4 or more path overhead processors), separate interfaces will increase the pin count significantly. Another disadvantage of such a conventional approach is the need for two additional separate sets of shift registers for the receive side and two separate sets of shift registers for the transmit side.